The present invention relates generally to a computer implemented method for electronic design automation. More specifically, the present invention relates to selecting cells and/or tiles for congestion reduction after initial placement of the library cells.
Designing integrated circuits is a process that grows in complexity as the feature sizes of circuits shrink from one design generation to the next. As the count of circuits grows on a given die size, the number of pins or conductors that need to be routed between logical elements grows at an inverse square relationship to the size of the smallest circuit feature. Accordingly, routing, and specifically detailed routing, between and among pins has grown complex over the years. Further complexity occurs because the number of design rules that limit the allowable geometries adds to the set of calculations necessary when employing computers to perform detailed routing.
A technology, or technology node, is a design constraint that sets a predetermined minimum width for conductors. A minimum permissible width is a lower threshold of the smallest wire or conductor agreed-on between the circuit designer and the fabricator of integrated circuits using the design of the circuit designer. The technology node is limited by factors such as lithography and vapor deposition accuracy expected in semiconductor manufacturing equipment. Since at nanometer scales, statistical variations may cause feature edges to alternatively be within or outside of tolerances, the technology node is a goal of the manufacturing process that may be determined to be met with near certainty. At a technology node, the fabricator makes assurances that a very low yield of defects will occur due to reasons of fabrication unintentionally making features larger or smaller than the minimum permissible width, despite a circuit design occasionally requiring minimum permissible widths. Similar to minimum permissible width for conductors, minimum permissible pin width can be defined for each technology as the minimum width of pins in a library cell.
A path or route is a geometric description of the interconnect between a set of pins or endpoints of one or more nets. A net is a subset of components in an integrated circuit design as well as the interconnection of the pins of the subset of components. Each path is associated with a path delay or timing delay. The path may pass through a net associated with a first component, and a net of a second component. The path can be a 2-pin net. Thus, the path may link two or more components together by including at least one endpoint or pin of each component. A pin is an input or an output wire to a component. A netlist describes all the components in a design, and describes how these components or pins on the components are interconnected. The netlist may be described in a text file that corresponds to the component. The netlist may be a derivative, through additional processing, of a file format that may be as described by Verilog®, VHSIC Hardware Design Language (VHDL), among other high-level design languages. Verilog is a trademark of Cadence Design Systems.
Detailed routing of paths or routes is computationally complex. Accordingly, this step of the design process may take days and does not assure that all nets in a design will be routable. When intractable, non-routable nets are discovered, many hours or days of delay may be incurred due to a partially-performed detailed routing, and potentially requiring the circuit designer to set up a detailed routing again with additional incremental changes.